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DATE
1997
IEEE
70views Hardware» more  DATE 1997»
13 years 9 months ago
Fast power loss calculation for digital static CMOS circuits
: In this paper, we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level...
Sergey Gavrilov, Alexey Glebov, S. Rusakov, David ...
DAC
2007
ACM
14 years 5 months ago
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
Lei Cheng, Deming Chen, Martin D. F. Wong