DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
CHARME
2005
Springer
13 years 10 months ago
2005
Springer
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
VLSID
2004
IEEE
14 years 4 months ago
2004
IEEE
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...