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FPGA
2008
ACM

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A novel FPGA logic block for improved arithmetic performance

13 years 6 months ago

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...

Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne

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