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ASPDAC
2006
ACM
128views Hardware» more  ASPDAC 2006»
13 years 8 months ago
A new test and characterization scheme for 10+ GHz low jitter wide band PLL
- This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We me...
Kazuhiko Miki, David Boerstler, Eskinder Hailu, Ji...