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    DATE
    1999
    IEEE
    86views Hardware» more  DATE 1999»
    Glitch Power Minimization by Gate Freezing
    13 years 9 months ago
    Glitch Power Minimization by Gate Freezing
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    This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally...
    Luca Benini, Giovanni De Micheli, Alberto Macii, E...
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