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GLVLSI
2009
IEEE
146views VLSI» more  GLVLSI 2009»
13 years 8 months ago
A reconfigurable stochastic architecture for highly reliable computing
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan...
GLVLSI
2009
IEEE
172views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Contact merging algorithm for efficient substrate noise analysis in large scale circuits
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
Michael Kadin, Sherief Reda, Augustus K. Uht
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
13 years 8 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Spatial and temporal design debug using partial MaxSAT
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
Yibin Chen, Sean Safarpour, Andreas G. Veneris, Jo...
GLVLSI
2009
IEEE
151views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Reliability aware NoC router architecture using input channel buffer sharing
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Mohammad Hossein Neishaburi, Zeljko Zilic
GLVLSI
2009
IEEE
132views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Multicast routing with dynamic packet fragmentation
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand
GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...