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GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
9 years 1 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
9 years 1 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
GLVLSI
2009
IEEE
201views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Glitch-free design for multi-threshold CMOS NCL circuits
In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into async...
Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia D...
GLVLSI
2009
IEEE
174views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Terahertz sensing technology
Michael S. Shur
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Design tools for emerging technologies
The rapidly expanding diversity of technology available at the nanoscale is disrupting the existing transistorcentric microelectronics design paradigm, resulting in nearly decade-l...
Jacob White
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
9 years 7 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
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