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IAJIT
2010
140views more  IAJIT 2010»
9 years 4 months ago
HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji...
BCS
2008
9 years 7 months ago
A Hardware Relaxation Paradigm for Solving NP-Hard Problems
Digital circuits with feedback loops can solve some instances of NP-hard problems by relaxation: the circuit will either oscillate or settle down to a stable state that represents...
Paul Cockshott, Andreas Koltes, John O'Donnell, Pa...
CHES
2006
Springer
158views Cryptology» more  CHES 2006»
9 years 9 months ago
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrolle...
Manuel Koschuch, Joachim Lechner, Andreas Weitzer,...
DAC
2004
ACM
9 years 9 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
FPL
2007
Springer
136views Hardware» more  FPL 2007»
10 years 1 days ago
A Load/Store Unit for a Memcpy Hardware Accelerator
Recently, a dedicated hardware accelerator was proposed that works in conjunction with caches found next to modern-day microprocessors, to speedup the commonly utilized memcpy ope...
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong
IPPS
2008
IEEE
10 years 9 days ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
CSE
2009
IEEE
10 years 20 days ago
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
Sebastian Hessel, David Szczesny, Shadi Traboulsi,...
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