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    ISLPED
    1999
    ACM
    131views Hardware» more  ISLPED 1999»
    Challenges in clockgating for a low power ASIC methodology
    13 years 9 months ago
    Challenges in clockgating for a low power ASIC methodology
    Download  www.cs.utah.edu
    Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
    David Garrett, Mircea R. Stan, Alvar Dean
    claim paper
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