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HPCA
1997
IEEE
9 years 11 months ago
Multiple Branch and Block Prediction
Steven Wallace, Nader Bagherzadeh
HPCA
1997
IEEE
9 years 11 months ago
Control Flow Speculation in Multiscalar Processors
Quinn Jacobson, Steve Bennett, Nikhil Sharma, Jame...
HPCA
1997
IEEE
10 years 10 days ago
Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks
ÐIn this paper, we study distributed path reservation protocols for multiplexed all-optical interconnection networks. The path reservation protocols negotiate the reservation and ...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
HPCA
1997
IEEE
10 years 10 days ago
Datapath Design for a VLIW Video Signal Processor
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S....
HPCA
1997
IEEE
10 years 10 days ago
ATM and Fast Ethernet Network Interfaces for User-Level Communication
Fast Ethernet and ATM are two attractive network technologies for interconnecting workstation clusters for parallel and distributed computing. This paper compares network interfac...
Matt Welsh, Anindya Basu, Thorsten von Eicken
HPCA
1997
IEEE
10 years 10 days ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross
HPCA
1997
IEEE
10 years 10 days ago
Design Issues and Tradeoffs for Write Buffers
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
Kevin Skadron, Douglas W. Clark
HPCA
1997
IEEE
10 years 10 days ago
A Performance Comparison of Hierarchical Ring- and Mesh-Connected Multiprocessor Networks
This paper compares the performance of hierarchical ring- and mesh-connected wormhole routed shared memory multiprocessor networks in a simulation study. Hierarchical rings are in...
Govindan Ravindran, Michael Stumm
HPCA
1997
IEEE
10 years 10 days ago
Software-Managed Address Translation
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in ...
Bruce L. Jacob, Trevor N. Mudge
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