Software-Managed Address Translation

In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that softwaremanaged address translation is just as efficient as hardware-managed address translation, and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms.

• Type: Conference
• Year: 1997
• Where: HPCA
• Authors: Bruce L. Jacob, Trevor N. Mudge
• Keywords: Address Translation, Distributed And Parallel Computing, HPCA 1997, Software-managed Address Translation, Softwaremanaged Address Translation