ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...