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ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 1 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCD
2001
IEEE
86views Hardware» more  ICCD 2001»
14 years 1 months ago
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement
Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aima...
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
14 years 1 months ago
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...
Martin Saint-Laurent, Madhavan Swaminathan, James ...
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
14 years 1 months ago
Improved ZDN-arithmetic for Fast Modulo Multiplication
In 1987 Sedlak proposed a modulo multiplication algorithm which is suitable for smart card implementation due to it’s low latency time. It is based on ZDN (zwei_drittel_N) arith...
Hagen Ploog, Sebastian Flügel, Dirk Timmerman...
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
14 years 1 months ago
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications
We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permut...
John Patrick McGregor, Ruby B. Lee
ICCD
2001
IEEE
105views Hardware» more  ICCD 2001»
14 years 1 months ago
Timing Characterization of Dual-edge Triggered Flip-flops
A novel timing characterization for dual-edge triggered flip-flops is presented in this paper. This characterization takes into account the real overhead taken from the clock cycl...
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
ICCD
2001
IEEE
98views Hardware» more  ICCD 2001»
14 years 1 months ago
Voltage Scaling for Energy Minimization with QoS Constraints
Ali Manzak, Chaitali Chakrabarti
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 1 months ago
Pre-routing Estimation of Shielding for RLC Signal Integrity
The formiila-based I<,JJ model is a figiire of merit for the inductive coirpling, and has been used to solve the simrrltaneoris shield insertion and net ordering (SINO) and sim...
James D. Z. Ma, Arvind Parihar, Lei He