High-Level Power Modeling of CPLDs and FPGAs

In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then use an adaptive regression method to model the FPGA power consumption. Such a high-level model can be used in the inner loop of a system-level synthesis tool to estimate the power consumed by different FPGA resources for different potential system-level synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our high-level power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1% compared to low-level FPGA power simulation methods.

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Li Shang, Niraj K. Jha
• Keywords: FPGA Power Consumption, FPGA Power Dissipation, Hardware, ICCD 2001, Low-level Fpga Power