Sciweavers

ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 1 months ago
Routed Inter-ALU Networks for ILP Scalability and Performance
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
Karthikeyan Sankaralingam, Vincent Ajay Singh, Ste...
ICCD
2003
IEEE
115views Hardware» more  ICCD 2003»
14 years 1 months ago
Reducing Compilation Time Overhead in Compiled Simulators
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
Mehrdad Reshadi, Nikil D. Dutt
ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
14 years 1 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
Peter Petrov, Alex Orailoglu
ICCD
2003
IEEE
107views Hardware» more  ICCD 2003»
14 years 1 months ago
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches
Embedded processors like Intel’s XScale use dynamic branch prediction to improve performance. Due to the presence of context switches, the accuracy of these predictors is reduce...
Sudeep Pasricha, Alexander V. Veidenbaum
ICCD
2003
IEEE
134views Hardware» more  ICCD 2003»
14 years 1 months ago
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk
Analyzing the effect of crosstalk on delay is critical for high performance circuits. The major bottleneck in performing crosstalkinduced delay analysis is the high computational ...
Venkatesan Rajappan, Sachin S. Sapatnekar
ICCD
2003
IEEE
140views Hardware» more  ICCD 2003»
14 years 1 months ago
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
NAND flash memory has become an indispensable component in embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cos,t and high d...
Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim...
ICCD
2003
IEEE
105views Hardware» more  ICCD 2003»
14 years 1 months ago
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
14 years 1 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 1 months ago
Interface Synthesis using Memory Mapping for an FPGA Platform
Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K...
ICCD
2003
IEEE
140views Hardware» more  ICCD 2003»
14 years 1 months ago
Reducing Multimedia Decode Power using Feedback Control
Despite recent advances, battery life continues to be a limiting factor in mobile multimedia systems. Signiï¬cant energy savings can be achieved by adapting systems at runtime to...
Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadr...