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IMS
2000
125views Hardware» more  IMS 2000»
13 years 8 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
IMS
2000
145views Hardware» more  IMS 2000»
13 years 8 months ago
FlexCache: A Framework for Flexible Compiler Generated Data Caching
Csaba Andras Moritz, Matthew Frank, Saman P. Amara...
IMS
2000
123views Hardware» more  IMS 2000»
13 years 8 months ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...
IMS
2000
115views Hardware» more  IMS 2000»
13 years 8 months ago
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips
Michael C. Huang, Jose Renau, Seung-Moon Yoo, Jose...