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INTEGRATION
2008
127views more  INTEGRATION 2008»
9 years 6 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
INTEGRATION
2006
102views more  INTEGRATION 2006»
9 years 8 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
INTEGRATION
2006
41views more  INTEGRATION 2006»
9 years 8 months ago
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
David Atienza, Stylianos Mamagkakis, Francesco Pol...
INTEGRATION
2006
74views more  INTEGRATION 2006»
9 years 8 months ago
Multilevel routing with jumper insertion for antenna avoidance
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
INTEGRATION
2006
82views more  INTEGRATION 2006»
9 years 8 months ago
On whitespace and stability in physical synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...
Saurabh N. Adya, Igor L. Markov, Paul G. Villarrub...
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