A parameterized graph-based framework for high-level test synthesis

Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. In our register allocation method, several high-level testability parameters including sequential depth, sequential loop, and controllability/ observability are considered. Our experiments show using this register allocation method results in significant improvement in automatic test pattern generation time and fault coverage. r 2005 Elsevier B.V. All rights reserved.

• Type: Journal
• Year: 2006
• Where: INTEGRATION
• Authors: Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh
• Keywords: Fault Coverage, INTEGRATION 2006, Register Allocation Method, Testability