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ISCA
1993
IEEE
113views Hardware» more  ISCA 1993»
10 years 3 months ago
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History
Recent attention to speculative execution as a mechanism for increasing performance of single instruction streams has demanded substantially better branch prediction than what has...
Tse-Yu Yeh, Yale N. Patt
ISCA
1993
IEEE
115views Hardware» more  ISCA 1993»
10 years 3 months ago
Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays
Parity encoded redundant disk arrays provide highly reliable, cost effective secondary storage with high performance for read accesses and large write accesses. Their performance ...
Daniel Stodolsky, Garth A. Gibson, Mark Holland
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
10 years 3 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
10 years 3 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
ISCA
1993
IEEE
112views Hardware» more  ISCA 1993»
10 years 3 months ago
Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors
The distribution of resources among processors, memory and caches is a crucial question faced by designers of large-scale parallel machines. If a machine is to solve problems with...
Edward Rothberg, Jaswinder Pal Singh, Anoop Gupta
ISCA
1993
IEEE
111views Hardware» more  ISCA 1993»
10 years 3 months ago
Cache Write Policies and Performance
Norman P. Jouppi
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
10 years 3 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
Jerome C. Huck, Jim Hays
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
10 years 3 months ago
Transactional Memory: Architectural Support for Lock-Free Data Structures
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
Maurice Herlihy, J. Eliot B. Moss
ISCA
1993
IEEE
117views Hardware» more  ISCA 1993»
10 years 3 months ago
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
We evaluate the e ect of processor speed, network bandwidth, and software overhead on the performance of release-consistent software distributed shared memory. We examine ve di er...
Sandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, ...
ISCA
1993
IEEE
92views Hardware» more  ISCA 1993»
10 years 3 months ago
The Detection and Elimination of Useless Misses in Multiprocessors
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, ...
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