Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
ISCA
1997
IEEE
119views Hardware» more  ISCA 1997»
11 years 8 months ago
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference
Deeply pipelined, superscalar processors require accurate branch prediction to achieve high performance. Two-level branch predictors have been shown to achieve high prediction acc...
Eric Sprangle, Robert S. Chappell, Mitch Alsup, Ya...
ISCA
1997
IEEE
78views Hardware» more  ISCA 1997»
11 years 8 months ago
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardwa...
Pierre Michaud, André Seznec, Richard Uhlig
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
11 years 8 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
11 years 8 months ago
Target Prediction for Indirect Jumps
As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be th...
Po-Yung Chang, Eric Hao, Yale N. Patt
ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
11 years 9 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
ISCA
1997
IEEE
114views Hardware» more  ISCA 1997»
11 years 9 months ago
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
Sriram Vajapeyam, Tulika Mitra
ISCA
1997
IEEE
90views Hardware» more  ISCA 1997»
11 years 9 months ago
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...
Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abd...
ISCA
1997
IEEE
104views Hardware» more  ISCA 1997»
11 years 9 months ago
Complexity-Effective Superscalar Processors
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
Subbarao Palacharla, Norman P. Jouppi, James E. Sm...
ISCA
1997
IEEE
113views Hardware» more  ISCA 1997»
11 years 9 months ago
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture
This work provides a systematic study of the impact of communication performance on parallelapplications in a high performance network of workstations. We develop an experimental ...
Richard P. Martin, Amin Vahdat, David E. Culler, T...
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
11 years 9 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
books