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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
13 years 9 months ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens
ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
13 years 9 months ago
On the value locality of store instructions
Value locality, a recently discovered program attribute that describes the likelihood of the recurrence of previously-seen program values, has been studied enthusiastically in the...
Kevin M. Lepak, Mikko H. Lipasti
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
13 years 9 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
13 years 9 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
13 years 9 months ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
13 years 9 months ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...
ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
13 years 9 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
ISCA
2000
IEEE
91views Hardware» more  ISCA 2000»
13 years 9 months ago
Performance analysis of the Alpha 21264-based Compaq ES40 system
This paper evaluates performance characteristics of the Compaq ES40 shared memory multiprocessor. The ES40 system contains up to four Alpha 21264 CPU’s together with a high-perf...
Zarka Cvetanovic, Richard E. Kessler
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
13 years 9 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ISCA
2000
IEEE
117views Hardware» more  ISCA 2000»
13 years 9 months ago
Wattch: a framework for architectural-level power analysis and optimizations
David Brooks, Vivek Tiwari, Margaret Martonosi