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ISCA
2006
IEEE
150views Hardware» more  ISCA 2006»
13 years 10 months ago
Spatial Memory Streaming
Prior research indicates that there is much spatial variation in applications' memory access patterns. Modern memory systems, however, use small fixed-size cache blocks and a...
Stephen Somogyi, Thomas F. Wenisch, Anastassia Ail...
ISCA
2006
IEEE
151views Hardware» more  ISCA 2006»
13 years 10 months ago
The BlackWidow High-Radix Clos Network
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with...
Steve Scott, Dennis Abts, John Kim, William J. Dal...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
13 years 10 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
ISCA
2006
IEEE
114views Hardware» more  ISCA 2006»
13 years 10 months ago
Ensemble-level Power Management for Dense Blade Servers
One of the key challenges for high-density servers (e.g., blades) is the increased costs in addressing the power and heat density associated with compaction. Prior approaches have...
Parthasarathy Ranganathan, Phil Leech, David E. Ir...
ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
13 years 10 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
ISCA
2006
IEEE
107views Hardware» more  ISCA 2006»
13 years 10 months ago
Distributed Arithmetic on a Quantum Multicomputer
We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and t...
Rodney Van Meter, Kae Nemoto, W. J. Munro, Kohei M...
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
13 years 10 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
13 years 10 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
13 years 10 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
ISCA
2006
IEEE
120views Hardware» more  ISCA 2006»
13 years 10 months ago
Interconnection Networks for Scalable Quantum Computers
We show that the problem of communication in a quantum computer reduces to constructing reliable quantum channels by distributing high-fidelity EPR pairs. We develop analytical m...
Nemanja Isailovic, Yatish Patel, Mark Whitney, Joh...