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ISCA
2006
IEEE
114views Hardware» more  ISCA 2006»
10 years 11 months ago
Using System-on-a-Programmable-Chip Technology to Design Embedded Systems
This paper describes the tools, techniques, and devices used to design embedded products with system
James O. Hamblen, Tyson S. Hall
ISCA
2006
IEEE
92views Hardware» more  ISCA 2006»
10 years 11 months ago
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cr...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
10 years 11 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
10 years 11 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
10 years 11 months ago
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
ISCA
2006
IEEE
145views Hardware» more  ISCA 2006»
10 years 11 months ago
Techniques for Multicore Thermal Management: Classification and New Exploration
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
James Donald, Margaret Martonosi
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
11 years 5 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
11 years 5 months ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
11 years 5 months ago
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
Chenyu Yan, Daniel Englender, Milos Prvulovic, Bri...
ISCA
2006
IEEE
121views Hardware» more  ISCA 2006»
11 years 5 months ago
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors
A simple and low-cost approach to supporting snoopy cache coherence is to logically embed a unidirectional ring in the network of a multiprocessor, and use it to transfer snoop me...
Karin Strauss, Xiaowei Shen, Josep Torrellas
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