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    ISLPED
    1995
    ACM
    193views Hardware» more  ISLPED 1995»
    Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
    13 years 8 months ago
    Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
    Download  eda.ee.ucla.edu
    We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
    Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
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    ISLPED
    1995
    ACM
    134views Hardware» more  ISLPED 1995»
    High-throughput and low-power DSP using clocked-CMOS circuitry
    13 years 8 months ago
    High-throughput and low-power DSP using clocked-CMOS circuitry
    Download  www.cecs.uci.edu
    We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
    Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
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