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ISLPED
1996
ACM
100views Hardware» more  ISLPED 1996»
12 years 2 months ago
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods...
Tohru Ishihara, Hiroto Yasuura
ISLPED
1996
ACM
80views Hardware» more  ISLPED 1996»
12 years 2 months ago
Implementation of a micro power 15-bit "floating-point" A/D converter
Micro power A/D converter are required for power sensitive, battery-operated equipment such as hearing aids. This paper overviews the principles of the 15-bit 'Floating point...
L. Grisoni, Alexandre Heubi, Peter Balsiger, Faust...
ISLPED
1996
ACM
89views Hardware» more  ISLPED 1996»
12 years 2 months ago
A novel methodology for transistor-level power estimation
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, ...
ISLPED
1996
ACM
143views Hardware» more  ISLPED 1996»
12 years 2 months ago
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Ko...
ISLPED
1996
ACM
79views Hardware» more  ISLPED 1996»
12 years 2 months ago
Micro power "relative precision" 13 bits cyclic RSD A/D converter
Alexandre Heubi, Peter Balsiger, Fausto Pellandini
ISLPED
1996
ACM
76views Hardware» more  ISLPED 1996»
12 years 2 months ago
Comparison of high speed voltage-scaled conventional and adiabatic circuits
The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energy-recovering logic families. Usin...
David J. Frank
ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
12 years 2 months ago
Simultaneous buffer and wire sizing for performance and power optimization
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
ISLPED
1996
ACM
89views Hardware» more  ISLPED 1996»
12 years 2 months ago
Low power systems for wireless microsensors
K. Bult, Amit Burstein, D. Chang, Michael J. Dong,...
ISLPED
1996
ACM
91views Hardware» more  ISLPED 1996»
12 years 2 months ago
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices
This paper presents an accurate model for the evaluation of the CMOS short-circuit power dissipation for shortchannel devices, on the basis of a CMOS inverter. The improvement of ...
Labros Bisdounis, Odysseas G. Koufopavlou, Spirido...
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