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ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
13 years 9 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ISPD
1999
ACM
106views Hardware» more  ISPD 1999»
13 years 9 months ago
Timing driven maze routing
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Sung-Woo Hur, Ashok Jagannathan, John Lillis
ISPD
1999
ACM
69views Hardware» more  ISPD 1999»
13 years 9 months ago
Interconnect thermal modeling for determining design limits on current density
Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo ...
ISPD
1999
ACM
94views Hardware» more  ISPD 1999»
13 years 9 months ago
Gate sizing with controlled displacement
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
ISPD
1999
ACM
77views Hardware» more  ISPD 1999»
13 years 9 months ago
Post-routing timing optimization with routing characterization
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
ISPD
1999
ACM
85views Hardware» more  ISPD 1999»
13 years 9 months ago
Optimal partitioners and end-case placers for standard-cell layout
We study alternatives to FM-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instan...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
ISPD
1999
ACM
83views Hardware» more  ISPD 1999»
13 years 9 months ago
Efficient solution of systems of orientation constraints
One subtask in constraint-driven placement is enforcing a set of orientation constraints on the devices being placed. Such constraints are created in order to, for example, implem...
Joseph L. Ganley
ISPD
1999
ACM
112views Hardware» more  ISPD 1999»
13 years 9 months ago
Arbitrary convex and concave rectilinear block packing using sequence-pair
The sequence-pair was proposed in 1994 as a representation of the packing of rectangles of general structure. Since then, there have been e orts to expand its applicability over s...
Kunihiro Fujiyoshi, Hiroshi Murata
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
13 years 9 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo