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ISPD
1999
ACM
127views Hardware» more  ISPD 1999»
10 years 8 months ago
Buffer insertion for clock delay and skew minimization
 Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
X. Zeng, D. Zhou, Wei Li
ISPD
1999
ACM
95views Hardware» more  ISPD 1999»
10 years 8 months ago
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Yanhong Yuan, Prithviraj Banerjee
ISPD
1999
ACM
92views Hardware» more  ISPD 1999»
10 years 8 months ago
Slicing floorplans with range constraint
Fung Yu Young, D. F. Wong
ISPD
1999
ACM
108views Hardware» more  ISPD 1999»
10 years 8 months ago
On the behavior of congestion minimization during placement
Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability accurately. In thi...
Maogang Wang, Majid Sarrafzadeh
ISPD
1999
ACM
92views Hardware» more  ISPD 1999»
10 years 8 months ago
Crosstalk constrained global route embedding
- Route Embedding, a new method for mitigating the impact of crosstalk, is presented. It modifies a set of global-route structures to prevent timing and noise-margin violations ca...
Phiroze N. Parakh, Richard B. Brown
ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
10 years 8 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
ISPD
1999
ACM
126views Hardware» more  ISPD 1999»
10 years 8 months ago
Partitioning by iterative deletion
Netlist partitioning is an important and well studied problem. In this paper, a linear time partitioning approach based on iterative deletion is presented. We use the partitioning...
Patrick H. Madden
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
10 years 8 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
ISPD
1999
ACM
88views Hardware» more  ISPD 1999»
10 years 8 months ago
Subwavelength optical lithography: challenges and impact on physical design
We review the implications of subwavelength optical lithography for new tools and ows in the interface between layout design and manufacturability. After discussing the necessity ...
Andrew B. Kahng, Y. C. Pati
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