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    ISPD
    2003
    ACM
    123views Hardware» more  ISPD 2003»
    3D thermal-ADI: an efficient chip-level transient thermal simulator
    13 years 9 months ago
    3D thermal-ADI: an efficient chip-level transient thermal simulator
    Download  www.cecs.uci.edu
    Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Che...
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    ISPD
    2003
    ACM
    133views Hardware» more  ISPD 2003»
    Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
    13 years 9 months ago
    Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
    Download  vlsi.ece.wisc.edu
    In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
    Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
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    ISPD
    2003
    ACM
    123views Hardware» more  ISPD 2003»
    A complete design for power methodology and flow for large ASICs
    13 years 9 months ago
    A complete design for power methodology and flow for large ASICs
    Download  www.cecs.uci.edu
    Raymond X. Nijssen, Ed P. Huijbregts
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    ISPD
    2003
    ACM
    80views Hardware» more  ISPD 2003»
    There is life left in ASICs
    13 years 9 months ago
    There is life left in ASICs
    Download  www.cs.york.ac.uk
    Leon Stok, John M. Cohn
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    ISPD
    2003
    ACM
    79views Hardware» more  ISPD 2003»
    Floorplanning of pipelined array modules using sequence pairs
    13 years 9 months ago
    Floorplanning of pipelined array modules using sequence pairs
    Download  www.cecs.uci.edu
    Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
    Matthew Moe, Herman Schmit
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    ISPD
    2003
    ACM
    92views Hardware» more  ISPD 2003»
    An architectural exploration of via patterned gate arrays
    13 years 9 months ago
    An architectural exploration of via patterned gate arrays
    Download  www.ece.cmu.edu
    Chetan Patel, Anthony Cozzie, Herman Schmit, Lawre...
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    ISPD
    2003
    ACM
    110views Hardware» more  ISPD 2003»
    Explicit gate delay model for timing evaluation
    13 years 9 months ago
    Explicit gate delay model for timing evaluation
    Download  www.cecs.uci.edu
    Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
    Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
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    ISPD
    2003
    ACM
    103views Hardware» more  ISPD 2003»
    An integrated floorplanning with an efficient buffer planning algorithm
    13 years 9 months ago
    An integrated floorplanning with an efficient buffer planning algorithm
    Download  www.cecs.uci.edu
    Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
    Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
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    ISPD
    2003
    ACM
    106views Hardware» more  ISPD 2003»
    Process variation aware clock tree routing
    13 years 9 months ago
    Process variation aware clock tree routing
    Download  dropzone.tamu.edu
    Bing Lu, Jiang Hu, Gary Ellis, Haihua Su
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    ISPD
    2003
    ACM
    75views Hardware» more  ISPD 2003»
    Layout impact of resolution enhancement techniques: impediment or opportunity?
    13 years 9 months ago
    Layout impact of resolution enhancement techniques: impediment or opportunity?
    Download  www.ispd.cc
    Lars Liebmann
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