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ISPD
2003
ACM
123views Hardware» more  ISPD 2003»
9 years 4 months ago
3D thermal-ADI: an efficient chip-level transient thermal simulator
Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Che...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
9 years 4 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
ISPD
2003
ACM
123views Hardware» more  ISPD 2003»
9 years 4 months ago
A complete design for power methodology and flow for large ASICs
Raymond X. Nijssen, Ed P. Huijbregts
ISPD
2003
ACM
80views Hardware» more  ISPD 2003»
9 years 4 months ago
There is life left in ASICs
Leon Stok, John M. Cohn
ISPD
2003
ACM
79views Hardware» more  ISPD 2003»
9 years 4 months ago
Floorplanning of pipelined array modules using sequence pairs
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
Matthew Moe, Herman Schmit
ISPD
2003
ACM
92views Hardware» more  ISPD 2003»
9 years 4 months ago
An architectural exploration of via patterned gate arrays
Chetan Patel, Anthony Cozzie, Herman Schmit, Lawre...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
9 years 4 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
9 years 4 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
ISPD
2003
ACM
106views Hardware» more  ISPD 2003»
9 years 4 months ago
Process variation aware clock tree routing
Bing Lu, Jiang Hu, Gary Ellis, Haihua Su
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