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ITC
1994
IEEE
136views Hardware» more  ITC 1994»
11 years 9 months ago
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza ...
ITC
1994
IEEE
82views Hardware» more  ITC 1994»
11 years 9 months ago
Making the Circular Self-Test Path Technique Effective for Real Circuits
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
ITC
1994
IEEE
151views Hardware» more  ITC 1994»
11 years 9 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey
ITC
1994
IEEE
111views Hardware» more  ITC 1994»
11 years 9 months ago
Simulation Results of an Efficient Defect-Analysis Procedure
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...
Olaf Stern, Hans-Joachim Wunderlich
ITC
1994
IEEE
99views Hardware» more  ITC 1994»
11 years 9 months ago
Transparent Memory Testing for Pattern-Sensitive Faults
Mark G. Karpovsky, Vyacheslav N. Yarmolik
ITC
1994
IEEE
90views Hardware» more  ITC 1994»
11 years 9 months ago
Defect Classes - An Overdue Paradigm for CMOS IC
: The IC test industry has struggled .for more than 30years to establish a test approach that would guarantee a low defect level to the customer. Wepropose a comprehensive strategy...
Charles F. Hawkins, Jerry M. Soden, Alan W. Righte...
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