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ITC
1994
IEEE

Automated Logic Synthesis of Random-Pattern-Testable Circuits

10 years 7 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken in this paper is to consider random pattern testability during logic synthesis. An automated logic synthesis procedure is presented which takes as an input a two-level representation of a circuit and a constraint on the minimum fault detection probability (threshold below which faults are considered r.p.r.) and generates a multilevel implementation that satisfies the constraint while minimizing the literal count. The procedure identifies r.p.r. faults and attempts to "eliminate" them through algebraic factoring. If that is not possible, then test points are inserted during the synthesis process in a way that minimizes the number of test points that are required. Results are shown for benchmark circuits which indicate that the proposed procedure can generally reduce the random pattern test length by...
Nur A. Touba, Edward J. McCluskey
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1994
Where ITC
Authors Nur A. Touba, Edward J. McCluskey
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