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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
13 years 10 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...