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ICCAD
1994
IEEE
121views Hardware» more  ICCAD 1994»
10 years 1 months ago
A cell-based power estimation in CMOS combinational circuits
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
CTRSA
2005
Springer
88views Cryptology» more  CTRSA 2005»
10 years 3 months ago
Side-Channel Leakage of Masked CMOS Gates
There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per cloc...
Stefan Mangard, Thomas Popp, Berndt M. Gammel
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
10 years 3 months ago
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the en...
Kris Tiri, Ingrid Verbauwhede
ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
10 years 6 months ago
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
Saraju P. Mohanty, Elias Kougianos
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