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ICCAD
1994
IEEE

A cell-based power estimation in CMOS combinational circuits

11 years 5 months ago
A cell-based power estimation in CMOS combinational circuits
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. Based on the model, a Cell-Based Power Estimation (CBPE) method is developed to estimate the power dissipation in CMOS combinational circuits. In our technique, we first construct a modified state transition graph called STGPE to model the power consumption behavior of a logic gate. Then, according to the input signal probabilities and transition densities of the logic gate, we perform an efficient method to estimate the expected activity number of each edge in the STGPE. Finally, the energy consumption of a logic gate is calculated by summing the energy consumptions of each edge in STGPE. For a set of benchmark circuits, experimental results show that the power dissipation estimated by CBPE is on average within 10-percent errors as compared to the exact SPICE simulation while the CPU time is more ...
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1994
Where ICCAD
Authors Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
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