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    VLSID
    2005
    IEEE
    158views VLSI» more  VLSID 2005»
    Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
    14 years 5 months ago
    Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
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    This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
    C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
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