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IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
9 years 7 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
COGSCI
2007
79views more  COGSCI 2007»
10 years 4 months ago
Contextualizing Counterintuitiveness: How Context Affects Comprehension and Memorability of Counterintuitive Concepts
A number of anthropologists have argued that religious concepts are minimally counterintuitive and that this gives them mnemic advantages. This paper addresses the question of why...
M. Afzal Upala, Lauren O. Gonce, Ryan D. Tweney, D...
IJES
2008
83views more  IJES 2008»
10 years 4 months ago
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures
Reconfigurable ALU Array (RAA) architectures--representing a popular class of Coarse-grained Reconfigurable Architectures--are gaining in popularity especially for media applicati...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
ARCS
2008
Springer
10 years 6 months ago
Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment
Abstract. A major problem considering parallel computing is maintaining memory consistency and coherency, and ensuring ownership and access rights. These problems mainly arise from...
Rainer Buchty, Oliver Mattes, Wolfgang Karl
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
10 years 8 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
10 years 8 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
FPL
1998
Springer
99views Hardware» more  FPL 1998»
10 years 8 months ago
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators
This paper discusses the memory interface of custom computing machines. We present a high speed parallel memory for the MoM-PDA machine, which is based on the Xputer paradigm. The ...
Reiner W. Hartenstein, Michael Herz, Thomas Hoffma...
CODES
2000
IEEE
10 years 8 months ago
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
SIPEW
2009
Springer
127views Hardware» more  SIPEW 2009»
10 years 9 months ago
Investigating Cache Parameters of x86 Family Processors
Abstract. The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance ...
Vlastimil Babka, Petr Tuma
MTDT
2002
IEEE
108views Hardware» more  MTDT 2002»
10 years 9 months ago
A Fault Modeling Technique to Test Memory BIST Algorithms
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil ...
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