Sciweavers

ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
11 years 11 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
PLDI
2011
ACM
13 years 5 days ago
A case for an SC-preserving compiler
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...
CORR
2011
Springer
165views Education» more  CORR 2011»
13 years 4 months ago
The Impact of Memory Models on Software Reliability in Multiprocessors
The memory consistency model is a fundamental system property characterizing a multiprocessor. The relative merits of strict versus relaxed memory models have been widely debated ...
Alexander Jaffe, Thomas Moscibroda, Laura Effinger...
TC
1998
13 years 9 months ago
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...
CORR
2010
Springer
140views Education» more  CORR 2010»
13 years 9 months ago
Window-Based Greedy Contention Management for Transactional Memory
r of Abstraction (invited lecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Barbara Liskov Fast Asynchronous Consensus with Optimal Resilience. . . . . . . . . . . ....
Gokarna Sharma, Brett Estrade, Costas Busch
CAV
2008
Springer
96views Hardware» more  CAV 2008»
13 years 11 months ago
Implied Set Closure and Its Application to Memory Consistency Verification
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...
Surender Baswana, Shashank K. Mehta, Vishal Powar
ICPP
1991
IEEE
14 years 26 days ago
Two Techniques to Enhance the Performance of Memory Consistency Models
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for mor...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
ICFEM
2004
Springer
14 years 2 months ago
Memory-Model-Sensitive Data Race Analysis
Abstract. We present a “memory-model-sensitive” approach to validating correctness properties for multithreaded programs. Our key insight is that by specifying both the inter-t...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom
SC
2005
ACM
14 years 2 months ago
Making Sequential Consistency Practical in Titanium
The memory consistency model in parallel programming controls the order in which operations performed by one thread may be observed by another. Language designers have been reluct...
Amir Kamil, Jimmy Su, Katherine A. Yelick
DSN
2006
IEEE
14 years 3 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin