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MICRO
2003
IEEE
99views Hardware» more  MICRO 2003»
12 years 4 months ago
Power-driven Design of Router Microarchitectures in On-chip Networks
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
MICRO
2003
IEEE
148views Hardware» more  MICRO 2003»
12 years 4 months ago
Fast Secure Processor for Inhibiting Software Piracy and Tampering
Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation...
Jun Yang 0002, Youtao Zhang, Lan Gao
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
12 years 4 months ago
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
Se-Hyun Yang, Babak Falsafi
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
12 years 4 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
12 years 4 months ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...
MICRO
2003
IEEE
116views Hardware» more  MICRO 2003»
12 years 4 months ago
Universal Mechanisms for Data-Parallel Architectures
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...
Karthikeyan Sankaralingam, Stephen W. Keckler, Wil...
MICRO
2003
IEEE
100views Hardware» more  MICRO 2003»
12 years 4 months ago
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...
MICRO
2003
IEEE
108views Hardware» more  MICRO 2003»
12 years 4 months ago
Reducing Design Complexity of the Load/Store Queue
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
Il Park, Chong-liang Ooi, T. N. Vijaykumar
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
12 years 4 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
12 years 4 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
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