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MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
13 years 9 months ago
Using Interaction Costs for Microarchitectural Bottleneck Analysis
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both (a) assign a ...
Brian A. Fields, Rastislav Bodík, Mark D. H...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
13 years 9 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
MICRO
2003
IEEE
155views Hardware» more  MICRO 2003»
13 years 9 months ago
Comparing Program Phase Detection Techniques
Detecting program phase changes accurately is an important aspect of dynamically adaptable systems. Three dynamic program phase detection techniques are compared – using instruc...
Ashutosh S. Dhodapkar, James E. Smith
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
13 years 9 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
MICRO
2003
IEEE
121views Hardware» more  MICRO 2003»
13 years 9 months ago
Exploiting Value Locality in Physical Register Files
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
Saisanthosh Balakrishnan, Gurindar S. Sohi
MICRO
2003
IEEE
88views Hardware» more  MICRO 2003»
13 years 9 months ago
Instruction Replication for Clustered Microarchitectures
Alex Aletà, Josep M. Codina, Antonio Gonz&a...
MICRO
2003
IEEE
132views Hardware» more  MICRO 2003»
13 years 9 months ago
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasa...
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
13 years 9 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
MICRO
2003
IEEE
95views Hardware» more  MICRO 2003»
13 years 9 months ago
Processor Acceleration Through Automated Instruction Set Customization
Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded appl...
Nathan Clark, Hongtao Zhong, Scott A. Mahlke