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MICRO
2005
IEEE
105views Hardware» more  MICRO 2005»
10 years 4 months ago
Incremental Commit Groups for Non-Atomic Trace Processing
We introduce techniques to support efficient non-atomic execution of very long traces on a new binary translation based, x86-64 compatible VLIW microprocessor. Incrementally comm...
Matt T. Yourst, Kanad Ghose
MICRO
2005
IEEE
170views Hardware» more  MICRO 2005»
10 years 4 months ago
The TM3270 Media-Processor
We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing, combined with embedded...
Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sa...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
10 years 4 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
MICRO
2005
IEEE
114views Hardware» more  MICRO 2005»
10 years 4 months ago
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
Sam S. Stone, Kevin M. Woley, Matthew I. Frank
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
10 years 4 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
10 years 4 months ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
MICRO
2005
IEEE
123views Hardware» more  MICRO 2005»
10 years 4 months ago
A Criticality Analysis of Clustering in Superscalar Processors
Clustered machines partition hardware resources to circumvent the cycle time penalties incurred by large, monolithic structures. This partitioning introduces a long inter-cluster ...
Pierre Salverda, Craig B. Zilles
MICRO
2005
IEEE
117views Hardware» more  MICRO 2005»
10 years 4 months ago
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into...
Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cr...
MICRO
2005
IEEE
140views Hardware» more  MICRO 2005»
10 years 4 months ago
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen,...
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
10 years 4 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
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