ICS
1995
Tsinghua U.
13 years 8 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
EUROPAR
2006
Springer
13 years 8 months ago
2006
Springer
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...
MICRO
1992
IEEE
13 years 8 months ago
1992
IEEE
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
MICRO
1996
IEEE
13 years 8 months ago
1996
IEEE
Much of the previous work on modulo scheduling has targeted numeric programs, in which, often, the majority of the loops are well-behaved loop-counter-based loops without early ex...
SCOPES
2005
Springer
13 years 10 months ago
2005
Springer
Software used in embedded systems is subject to strict timing and space constraints. The growing software complexity creates an urgent need for fast program execution under the co...
PLDI
2005
ACM
13 years 10 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
ICPPW
2006
IEEE
13 years 10 months ago
2006
IEEE
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
CC
2007
Springer
13 years 10 months ago
2007
Springer
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper describes a generalisation of modulo scheduling to parallelise loops for SpMT processors that exploits simultaneously both instruction-level parallelism and thread-leve...