ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V,
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes an optimum methodology for assigning supply and threshold voltages to modules in a CMOS circuit such that the overall energy consumption is minimized for a giv...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...