We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
An asynchronous router for QNoC (Quality-of service NoC) is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each leve...
Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cid...
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...