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PARELEC
2006
IEEE
13 years 10 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
13 years 10 months ago
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
Alexey Lopich, Piotr Dudek
IJCNN
2007
IEEE
13 years 10 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...