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FPL
2007
Springer
98views Hardware» more  FPL 2007»
13 years 6 months ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
FPL
2009
Springer
145views Hardware» more  FPL 2009»
13 years 9 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...