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SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
11 years 7 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
SBCCI
2005
ACM
122views VLSI» more  SBCCI 2005»
11 years 7 months ago
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Cavigl...
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
11 years 7 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
SBCCI
2005
ACM
86views VLSI» more  SBCCI 2005»
11 years 7 months ago
Ultra-low power CMOS cells for temperature sensors
Temperature sensors and voltage references require cells that generate both PTAT (Proportional To Absolute Temperature) and NTC (Negative Temperature Coefficient) voltages. We pre...
Conrado Rossi, Pablo Aguirre
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
11 years 7 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
SBCCI
2005
ACM
132views VLSI» more  SBCCI 2005»
11 years 7 months ago
Design and power optimization of CMOS RF blocks operating in the moderate inversion region
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
Leonardo Barboni, Rafaella Fiorelli
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
11 years 7 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
SBCCI
2005
ACM
80views VLSI» more  SBCCI 2005»
11 years 7 months ago
On the design of very small transconductance OTAs with reduced input offset
In this paper it will be demonstrated, from the theory and measurements, that series-parallel (SP) mirrors allow building current copiers with copy factors of thousands, without d...
Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Mo...
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
11 years 7 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
SBCCI
2005
ACM
136views VLSI» more  SBCCI 2005»
11 years 7 months ago
Current mask generation: a transistor level security against DPA attacks
The physical implementation of cryptographic algorithms may leak to some attacker security information by the side channel data, as power consumption, timing, temperature or elect...
Daniel Mesquita, Jean-Denis Techer, Lionel Torres,...
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