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2005
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Design of a decompressor engine on a SPARC processor

11 years 5 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumption, due to an increase in the cache hit ratio. This paper proposes the design of a code decompressor engine for our dictionary-based method, embedding it into the Leon (SPARC V8) processor. Our design guarantees that the processor cycle-time is maintained and the decompression is performed on-the-fly. We have achieved a functional implementation on a FPGA, with compression ratios ranging from 72% to 88%, performance improvement as high as 45% and a reduction on energy consumption reaching 35%, validated through two real-world benchmarks suites: MediaBench and MiBench. We also explore some trade-offs between compression ratio and performance. Categories and Subject Descriptors B.3 [Hardware]: Memory Structures; C.3 [Special Purpose and Application Based Systems]: Real-time and Embedded Systems General Terms ...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where SBCCI
Authors Richard E. Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Wanderley Netto
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