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3DIC
2009
IEEE
120views Hardware» more  3DIC 2009»
13 years 11 months ago
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-a...
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuw...