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    EURODAC
    1995
    IEEE
    137views VHDL» more  EURODAC 1995»
    A formal non-heuristic ATPG approach
    13 years 8 months ago
    A formal non-heuristic ATPG approach
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    This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
    Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
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