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DFT
2008
IEEE
117views VLSI» more  DFT 2008»
13 years 11 months ago
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
Vikas Chandra, Robert C. Aitken