substantial instruction fetch

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MICRO
1995
IEEE

97views Hardware» more MICRO 1995»

Improving CISC instruction decoding performance using a fill unit

12 years 9 months ago

Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...

Mark Smotherman, Manoj Franklin

claim paper

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